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<@U016EM8L91B>, what frequency range is the PLL required to operate at? specified either as an input...
# analog-design
t
@Tim Edwards, what frequency range is the PLL required to operate at? specified either as an input range or output range. input probably better since we know the divider requirements
Also, you have specified a fractional divide in the feedback as 1:255 / 8, and then separately, an output divide as 1:8. Does this mean: A:
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---[VCO]---[ 1 / 8 ]-+-[ 1 / (1:8) ]---> out
                     |
----[ 1 / 1:255 ]----+
OR B:
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---[VCO]---[ 1 / (1:8) ]--+--> out
                          |
----[ 1 / 1:255 ]---------+
🌏 1
t
I'm trying to figure out your ASCII diagram above.. . . What I meant was that the VCO output is immediately split into two paths; the feedback path goes through a fractional-N divider with division values from 1 0/8 to 31 7/8; the output divider is just divide by 1 to 8. The implementation likely does not involve an actual divider for the feedback path, but just counts VCO output clock edges vs. input clock edges over long enough time to get a statistically meaningful measurement of the frequency that is equivalent to a fractional division value and pulses a charge pump up or down accordingly.
I should probably think it through more carefully and re-spec it accordingly, with a target rate for the VCO. Unlike the DCO, the VCO will have a more limited range, so a fractional divider might be warranted on the output as well.
t
I messed up my diagram. The way i see it is as follows: a fractional division in the feedback path amounts to something like 8bit/8, thich results in a freq. multiple of 8bit/8, and therefore a feedback divider counter which is 8-bit, and then an output divider fixed at 1/8 like so: ---[VCO]------------+-----[ 1 / 8 ]----->-[ 1 / (1:8) ]---> out | ----[ 1 / 1:255 ]----+
the bit at the end is then the additional output divider you mention
am i misunderstanding what you mean or does that make sense? basically the "fraction" being implemented as a feedback divide to get the numerator and the output divide of 1/8 to get the denominator of 8 such that you get the steps of 0.125
t
Maybe this is clearer?
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Except that the feedback divider + comparator is usually not implemented that way, but with a counter. . . basically a sigma-delta.
t
yes i see what you mean now
is the fractional feedback divider a hard requirement or can it be implemented as a forward integer divide and a feedback integer divide instead rather than a sigma-delta?
@Tim Edwards if im understanding this correctly you want essentially a frequency counter in the FB path to be compared to a desired count value e.g. lets say i want 2.5 cycles of the VCO for every cycle of the ref clock, half the time I would measure 2, and half the time I would measure 3, which after sigma-delta would average to 2.5 for the CP. the thing is with this architecture is you loose phase information and as such this sounds more like an FLL to me than a PLL. Am I wrong?
What I'm suggesting is a PLL architecture with the classic M/N realised by a PFD fed with a ref and an integer divide in the FB path, with another output divide to give the M/N phase-locked ratio
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@Tim Edwards please ignore my last two messages. I have since figured out exactly how to achieve what you're talking about
t
I'd like to state that the fractional divider was something considered for the DLL, which has a very wide tuning range; a fractional feedback divider can allow it to hit any output frequency with no gaps. Otherwise, a fractional feedback divider could help with finding a stable operating point if the simulated frequency and tuning range were way off, but I don't think it would normally be needed.
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