open-source-silicon.dev

What’s the expected input refclks of the PLL and the desired frequency range? I noticed a 10Mhz ref in one of the specs and USB 1.2 mentioned so that would be 48 MHz output at least at some total mult.

Yes, it occurred to me today that I never got around to specifying that.  <@U01H2JMLFLL> asked the same question in <#C016HUV935L|analog-design>.

We will have three potential clock sources now---the original CMOS clock, a 32kHz XO, and a 4-16MHz XO.  Not sure yet if the intent is to run the PLL off of one of them, or any of them.

<@U01FX91TEE8>:  Okay, I've discussed this with Andy and we've settled on a 96 MHz VCO +/- 10%, expected input reference 4, 12, or 16 MHz.  I split the output divider in the spec to two, so one can generate the 48 MHz for USB but the secondary divider can generate a slower clock for the CPU (in case the digital design team can't hit a 48 MHz spec for the CPU).

Not entirely sure about the +/-10% range.  I haven't worked enough with the varactors to know what they can hit.  The 96MHz use case is all exact frequencies, so the range doesn't have to be huge.  I'm not even sure if there's a good use case for the fractional divider.

That all does make the design easier - If this is a mostly internal use PLL, then fractional N makes less sense. I was thinking just a good old fashioned Type II Charge Pump PLL although I do worry about the Filt cap size.