Join the First Efabless Chipalooza Analog and Mixed-Signal Design Challenge Create new analog and mixed signal circuits or improve existing open-source designs to enhance the next generation of Caravel harness chip, aimed at IoT machine learning applications. Description: The next generation of Caravel harness chip will be a major enhancement of the existing Caravel chip, targeting IoT machine learning applications by giving the designer many more resources to choose from than a processor. IoT applications connect to the real world, so they need analog-to-digital and digital-to-analog conversion, signal conditioning (amplifiers, biasing, and filtering), analog signal processing, power management (to maintain ultra-low power consumption for battery-operated applications), temperature sensing, and more. In this design challenge, we invite designers to contribute their best circuit designs to fill out a list of competitive IP that SoC designers will find attractive for developing IoT machine learning applications on Caravel. The benefits of new analog and mixed-signal circuits will be multi-fold. Competitive designs will be made available on the next-generation Caravel architecture as resources for designers needing input from and output to the real world, signal conditioning, power management, and analog signal processing. At the same time, all designs will collectively become the first major open-source collection of analog and mixed-signal IP, to be available for re-use and enhancement, for academic, commercial, and personal use. Rules: 1. Efabless will provide a list of IP blocks that we want to have available for the next-generation Caravel. For each IP block, Efabless will provide a specification including performance metrics to meet, and a pinout for the block, and a maximum area in which the design must fit. 2. The list of IP blocks is available at this link: https://docs.google.com/spreadsheets/d/132YkMiYaM0iHML5feT1yWLQIvP-pCM0lCArM9f1LxhM 3. Designers will write up and submit a simple proposal declaring which IP block they propose to design, and what architecture they plan to use to meet the specification. Proposals will be reviewed and accepted on the basis of need and design team capability. Designers are encouraged to submit multiple proposals, as all blocks on the list need to be designed to make a competitive future Caravel harness. 4. For the assessment of design team capability: Designers must show in the proposal that they have a good understanding of analog circuit design and are familiar with the principles and limitations of the circuit architecture they have adopted for their design. 5. Designers will have a specific set of deliverables for each design review, including the proposal, then schematic and simulations, then layout and verification. 6. Specifications provided by Efabless are not necessarily final, and any design group may request a review of a specification if they believe that the specification is impossible to meet, or meeting a circuit specification will degrade the circuit perfomance in other ways. All specification changes must be approved by Efabless prior to the first design review. 7. All designs will be submitted in the form of an open-source git repository and must contain all required design files, the original specification, and datasheet with results and plots. The file structure of the repository will follow guidelines. No commercial tools may be used in the design and verification process. 8. Final deliverables include the GDS file of the circuit block layout and a datasheet with post-layout simulation results, in the public repository along with all design files needed to completely reproduce both the layout and simulated characterization results. 9. Designers will not integrate the block into a Caravel user project, but integration of multiple projects into one or more chipIgnite slots will be done by Efabless, with project grouping at the discretion of Efabless. The target tapeout date for integrated projects is the April 24 chipIgnite shuttle run closing date. (A detailed list of guidelines will be posted to this channel after the kick-off webinar.) Resources: We will provide a standard circuit review process, including proposal review, schematic review, layout review, and final sign-off. Throughout the period between the Chipalooza launch and the close of the shuttle run, there will be webinars on how to use the open source schematic and layout tools, and principles of good analog and mixed-signal design; and workshops for helping designers get through the process and make it to tapeout with a competitive, industry-standard design. Awards: Awards are staged throughout the challenge. Any design team that has their proposal accepted for the challenge will be awarded a Tiny Tapeout slot. If a design team completes the schematic and simulations pass all required specifcations, then a second Tiny Tapeout slot will be awarded. Each Tiny Tapeout slot is a $300 value. Any design team that completes the required post-layout deliverables, adheres to the guidelines, and meets the circuit specifications on schedule will be given a free quarter slot on a future chipIgnite shuttle run, to do anything they like, analog or digital*. A quarter chipIgnite slot is an approximately $2500 value. In addition, each design team will receive a development board and the packaged test chip from the April shuttle run that has their design on it. Design teams are expected to perform basic functional verification of their block on silicon, but are not expected to do full characterization. This is a challenge, not a competition. Teams compete against the design specification, not each other. (*Free slots are subject to availability; please reserve a space well in advance of a shuttle run closing date.)