open-source-silicon.dev

image.png

I tried to draw a schematic but when I pres netlist it prints "warning: wrong line layer" and also the entire mosfet isn't in the netlist

netlist:
```**.subckt untitled
v0 net3 GND 3
l1 net4 net2 10n
c0 net2 net1 1p m=1
r0 net1 GND 1k m=1
v1 net4 GND 3
**** begin user architecture code
**** end user architecture code
**.ends
.GLOBAL GND
.end```

untitled.sch

You're missing a connection to the "B" terminal of the transistor.  You probably got an error window when you hit "Netlist".  For an nFET, be sure to connect "B" down to ground.

I added a bulk connection but still getting `WARNING: wrong line layer` messages and no transistor in the netlist.
It makes me suspicious that the gate wire turns red but I have no idea why. If I delete it and draw a new one it becomes red again.
I suppose that means it's not on the "wire" layer, but why?
It's also really puzzling to me that such an error would completely omit the transistor.

When you netlist, xschem will flag problems by highlighting nets.
Use  `View -&gt; Show ERC Info Window` to see problems.

&gt; Packaged xschem versions are too old and they conflict with the one you are building from source.
You know it's possible to make releases and distro packages...

I just did apt install xschem... now I did a fresh git clone

Still no ERC window but somehow the netlist button seems to work and overall everything is less painful and broken

How about `View -&gt; Show/Hide -&gt; Show ERC Info Window`?