How does this project work? The intro video says participant has access to every design, yet it also says total of ~1000 digital gates for base tile. Also some designs need to use more tiles. Does this mean there are different designs on same tile (I see problems with this approach)? Or one gets different packages for different designs (with some bigger designs in different size packages)? How many packages are provided? Sorry if I misunderstood…And please confirm analog circuits (amplifier etc) will incur extra gds charge adder? Thanks.

Hi @Sam Lim, every customer who joins a Tiny Tapeout shuttle and wants to buy a chip will get the same chip as all other customers, and your design occupies a small part of that chip. Your order is for 1 packaged chip in total (plus other support PCBs). The total area of that chip (i.e. the total die area) is divided up, meaning that each customer pays to reserve a small portion of the divided area, for their own design. 1 "tile" is the smallest piece you can reserve in that total area, and it is big enough for a design of about 1000 digital gates. If you have a larger design, you can reserve more tiles that are next to each other, so you can fit more gates or other analog layouts.

Thank you for your answer. So this is different from the MPW project then, where each participant is a distinct design but gets some qty of packaged parts… If I understand correctly, TT combines gds’es from all participants into a combined design and a chip is made from this. After manufacture, each participant gets 1 chip/package plus support pcb. If something goes wrong (esd damage or perhaps design malfunction due to process variance, test mistakes etc), there is no recovery to check another package… Also the project must be able to select amongst all design entrants. For analog designs, wouldn’t it present issues due to signal loss etc ? Perhaps it is meant mainly for digital undertakings…Also what size package pin out is planned? Again pardon me if I did not describe the project right.

Yes, you are generally right on all points. Note that the pins all have some level of ESD protection. If your 1 chip was damaged or otherwise faulty, you might want to make sure you communicate with other people on the same shuttle to see if anyone is willing to test your design on their own equipment. There is a method on the chip to select which design you want to be active at any given time, and yes for analog designs there are some tradeoffs. The chip package is a QFN-64 with 0.5mm pin pitch, but it comes mounted on a breakout board with 2.54mm-pitch headers, and this plugs into the 'demo board' which is used for power, selecting the active design, and optionally interfacing with the chip using an RP2040.

Appreciate your help and patience to clarify. 👍 👊