Hello, I am looking for a guide on how to do the analog design for the caravel. I saw the github page for the caravel_user_project_analog. Are there videos that could be helpful in setting it up or creating a simple design? Thanks in advance!

Can you please specify your exact requirement where you are facing problem? There are no consolidated videos as such for analog design. Following playlists on efabless YT channel can be helpful to start doing analog design for caravel: https://youtube.com/playlist?list=PLZuGFJzpFksCG7p1yURxVo5lWHzeOoR9_&si=IugvZ93fq7rX7ylf https://youtube.com/playlist?list=PLZuGFJzpFksALPQKbX88_HvwNdGMgzoxy&si=E9zt5E-HW22hkwN_

Sorry for the very late response @vks. I am wondering if it is required to write the verilog model for any analog design. Is the user_analog_project_wrapper.gds enough for the caravan as well as a successful precheck run?

Besides

user_analog_project_wrapper.gds

you need to put your netlist in proper order and do some GPIO related settings in

user_define.v

file to meet precheck requirements. That is not a big task, enough reference available on channel to get guidance on that.