do you know what the problem with those signals is?

Working with broken vga signals is tricky. I wanted to slow down the clock to rule out issues like setup violations, but you can't feed a differently clocked vga signal to a display. So I tried reading it into a framebuffer and sending out at the correct vga rate, but apparently my fpga doesn't have enough ram for the vga framebuffer. Eventually I slowed it down a lot (from ~25 MHz pixel clock to ~12 kHz) and sent it over UART to my computer where I simulated the vga beam using pygame.

Some glitches remain at low speed, in particular the hsync one but also the red channel gets one pixel delay compared to blue, and the green channel gets kind of half a pixel delay.

Screenshot_20240105_151616.png,Screenshot_20240105_151940.png,Screenshot_20240105_154202.png,Screenshot_20240105_154243.png,Screenshot_20240105_154415.png

The glitches are deterministic and came from the letters being drawn, i.e. you can add up the hsync shifts for each letter in the row and you get the hsync pattern for the row. I haven't yet found how the font pattern translates to the hsync glitches, but I stitched together this image to visualize it:

joinmagrgb.png

There are some further glitches that disappeared when slowing down the clock (flickering between frames, hsync shift on blocks with color background, and some vsync shift that remains after correcting for hsync). I'm not sure how much of them comes from the chip and how much from my setup (asic -> fpga -> resistor ladder dac -> vga-to-hdmi adapter -> hdmi capture card -> pc). I'll try to find some way to capture the digital vga pins at the full ~25MHz, but first I'm more interested in whatever causes the hsync issues at low speed. It's not in the RTL verilog as I've tried that on the fpga and there it works glitch-free.

(Note to the screenshots: The horizontal blue line marks the current position of the beam. Translucent blue regions to the right and to the bottom mark the off-screen regions. The vertical green stripe is where hsync is asserted and the horizontal red line is where vsync is asserted. Some screenshots have correction for hsync while others don't - it should be obvious.)