Hello, I am learning digital ic design with openlane. I have created a PWM controller in which duty cycle can be controlled with 8bits. So the generated ic should have 6pins namely, Vcc, Vas, clk, rst , duty and pwm. Everything worked fine but whine I check the gods in klayout there are 13 pins namely, Vcc, Vas, clk, rst, pwm and 8 separate pins for duty. By what methods or techniques I can reduce those 8pins to 1.

you've created a 8-bit wide value in your verilog file:

input [Width-1:8] duty

that'll get turned into 8 separate pins, plus all the other ones you've defined which will result in 13 total