<@U01819B63HP> /<@U016EM8L91B> is there a "correct...
# xschem
t
@Stefan Schippers /@Tim Edwards is there a "correct" way of getting rid of these messages when ruining LVS?
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No property as found for device nfet_03v3
No property ad found for device nfet_03v3
No property ps found for device nfet_03v3
No property pd found for device nfet_03v3
Model ppolyf_u_1k pin 1 == 2
No property par1 found for device ppolyf_u_1k
No property pm found for device ppolyf_u_1k
No property par found for device ppolyf_u_1k
No property r found for device ppolyf_u_1k
Model ppolyf_u_1k pin 1 == 2
No property par1 found for device ppolyf_u_1k
No property pm found for device ppolyf_u_1k
No property r found for device ppolyf_u_1k
Model nfet_03v3 pin 1 == 3
No property par1 found for device nfet_03v3
t
No, there isn't, but I could easily put those statements after
if (Debug)
.
Strictly speaking, some of those don't need to be in the netgen setup file; for example,
par1
and
pm
appear never to be resistor properties, so they can be removed from the
property delete
in the setup. On the other hand,
as
,
ad
,
ps
, and
pd
are optional parameters that are usually defined in both schematic and layout extraction, so they can't just be removed from the setup. It makes more sense, though, that if the intent of the
property delete
command is to ignore properties that might or might not be in the netlist, then diagnostic output should only be made on request.
s
Netlists produced by xschem for gf180mcu are tested for simulation. It is definitely possible to modify the netlist for LVS using the option SImulation -> LVS -> LVS netlist and adding a
lvs_format
attribute to symbols. this is done in the
nfet
and
pfet
symbols to remove unneeded attributes (ad, as, pd, ps, nrd, nrs and others) that cause warnings while doing LVS comparison. For spice simulation a
nfet_03v3
mos will be netlisted as:
XM1 D G S B nfet_03v3 L=0.28u W=0.22u nf=1 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u' pd='2*int((nf+1)/2) * (W/nf + 0.18u)'
+ ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W' sa=0 sb=0 sd=0 m=1
while for LVS it will be like this:
M1 D G S B nfet_03v3 L=0.28u W=0.22u nf=1 m=1
That said I don't know where the
par1
,
pm
,
par
,
r
property warnings come from. May be these pop out in the expansion of the spice models (devices are described as sub circuits). If a different netlist rule for LVS must be added for the other components this can be done using the above mentioned
lvs_format
attribute
t
@Stefan Schippers: The property warnings all come from the netgen setup file. Some of the properties are left over from other foundry processes and should have been removed; they just got copied over and weren't removed because they have no effect other than a warning message.
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