Can someone comment on the maturity level of the thin oxide MOSFET models in the current release? I ran some basic OP/DC simulations and see unusually large overlap capacitances (in fact larger than the intrinsic caps). These values are for 5um wide p/n devices:

cgg           2.21224e-15           2.55264e-15
        cgs           2.00547e-15           2.40474e-15
      cgsol           2.63377e-15           3.19575e-15
      cgdol           2.42174e-15           3.02492e-15

Is this a reasonably accurate representation of the technology? Lastly, when I plot fT against gate bias, I observe a somewhat non-physical kink for the n-channel, see the bottom of this Jupyter notebook: https://github.com/bmurmann/Ngspice-on-Colab/blob/main/notebooks/IHP_SG13G2_VGS_sweep.ipynb

I just tran you NB in our latest image, same kink. Maybe Markus Müller can take a look? @Krzysztof Herman

@Boris Murmann thank you for reporting this issue. We will take a look at it. As for the more general question about the maturity level I do not have a clear answer. The models were translated from our commercial PDK into ngspice syntax. We have made some comparison between simulation results obtained using spectre and ngspice and the results were almost identical. Unfortunately we can not share it because of the license agreement. Since we have not tested extensively the models in all cases the feedback from the community is more than welcome.

@Boris Murmann One more thing: IHP also has raw device measurements in the repo, so maybe you want to check them as well: https://github.com/IHP-GmbH/IHP-Open-PDK/tree/main/ihp-sg13g2/libs.doc/meas/MOS