Any idea why i have OEB and LVS errors on precheck?

LVS is missing the verilog for these cells

cbx_1__0_ 
cbx_1__1_ 
cbx_1__2_
cby_0__1_ 
cby_1__1_
cby_2__1_ 
grid_clb 
grid_io_bottom
grid_io_left
grid_io_right
grid_io_top
sb_0__0_ 
sb_0__1_
sb_0__2_ 
sb_1__0_
sb_1__1_
sb_1__2_ 
sb_2__0_ 
sb_2__1_
sb_2__2_

You can add them to

LVS_VERILOG_FILES

in

lvs/user_project_wrapper/lvs_config.json

. Be sure to list children cells before parents.

I made the change son the LVS_VERILOG_FILES variable, but it continuous with the LVS error (i attache the .json file). i don't understand at all when you mention "Be sure to list children cells before parents." i understand it as respect the module hierarchy, but all are at the same hierarchy. Related to the OEB error, it was solved, thanks!

@Emilio Baungarten Can you share your most recent lvs log files again?

10_DEC_2023___15_37_41.zip

For LVS, there’s a pin mismatch. Do you why there is a

net131

pin in the layout?

net131                                                                            |(no matching pin)

For CVC, the following buffer outputs are fixed low. This may be a problem if the buffer inputs are ever high.

/Xinput1
/Xinput2
/Xinput3
/Xinput4
/Xinput5
/Xinput6
/Xinput7
/Xinput8
/Xinput9
/Xinput10
/Xinput11
/Xinput17
/Xinput18
/Xinput19
/Xinput20
/Xinput21

For OEB and possibly related to the CVC results above, most of your outputs are fixed low

gpio |   in   |   out  | analog |  oeb min/sim/max  | Message
   0  |        |    vss |        |   vdd/  vdd/  vdd | 
   1  |        |    vss |        |   vdd/  vdd/  vdd | 
   2  |        |    vss |        |   vdd/  vdd/  vdd |
   3  |        |    vss |        |   vdd/  vdd/  vdd |
   4  |        |    vss |        |   vdd/  vdd/  vdd |
   5  |      4 |    vss |        |   vdd/  vdd/  vdd |
   6  |      4 |    vss |        |   vdd/  vdd/  vdd |
   7  |      4 |    vss |        |   vdd/  vdd/  vdd |
   8  |      4 |    vss |        |   vdd/  vdd/  vdd |
   9  |      4 |    vss |        |   vdd/  vdd/  vdd |
  10  |      4 |    vss |        |   vdd/  vdd/  vdd |
  11  |      4 |    vss |        |   vdd/  vdd/  vdd |
  12  |      4 |    vss |        |   vdd/  vdd/  vdd |
  13  |      4 |    vss |        |   vdd/  vdd/  vdd |
  14  |      4 |    vss |        |   vdd/  vdd/  vdd |
  15  |      4 |    vss |        |   vdd/  vdd/  vdd |
  16  |      4 |    vss |        |   vdd/  vdd/  vdd |
  17  |      4 |    vss |        |   vdd/  vdd/  vdd |
  18  |      4 |    vss |        |   vdd/  vdd/  vdd |
  19  |      4 |    vss |        |   vdd/  vdd/  vdd |
  20  |      4 |    vss |        |   vdd/  vdd/  vdd |
  21  |        |    vss |        |   vss/  vss/  vss |
  22  |        |    vss |        |   vss/  vss/  vss |
  23  |        |    vss |        |   vss/  vss/  vss |
  24  |        |    vss |        |   vss/  vss/  vss |
  25  |        |    vss |        |   vss/  vss/  vss |
  26  |        |    vss |        |   vss/  vss/  vss |
  27  |        |    vss |        |   vss/  vss/  vss |
  28  |        |    vss |        |   vss/  vss/  vss |
  29  |        |    vss |        |   vss/  vss/  vss |
  30  |        |    vss |        |   vss/  vss/  vss |
  31  |        |    vss |        |   vss/  vss/  vss |
  32  |        |      2 |        |   vss/  vss/  vss |
  33  |      4 |    vss |        |   vdd/  vdd/  vdd |
  34  |      4 |    vss |        |   vdd/  vdd/  vdd |
  35  |      4 |    vss |        |   vdd/  vdd/  vdd |
  36  |      4 |    vss |        |   vdd/  vdd/  vdd |
  37  |      4 |    vss |        |   vdd/  vdd/  vdd |

In the user_project_wrapper.v the net 131 is connected to the la_data_out[50], i tried to give specific value to all inputs and outputs but the result is the same again with the net 131 mimatch.

//First these signals was undefined, then i defined but i got the same result
assign wbs_ack_o = 0;
assign wbs_dat_o[31:0] = 32'd0;
assign la_data_out[63:0] =64'd0;
assign user_irq = 0;
assign  io_out[37:33]=0;
assign  io_out[20:0]=21'd0;

LVS is showing a match for

la_data_out[50]

as a separate net. I don’t know why only

net131

is being extracted as port. I think there’s a config setting that will prevent openlane from labeling internal nets that might solve the problem. I don’t think the rtl to gdsii flow fails on port checks. Do you know why all your outputs are low?

I dont use the LA ports so i jut set it to low to have an specific value, this design is and FPGA and is conected directly to de GPIO port. GPIO[20:5] is set as input, GPIO[32:21] is set as output, GPIO[37:33] is set as input, I will look the config setting that coul solve that error.

I think its

"MAGIC_DEF_LABELS": 0

the default is

1

. Your GPIO[31:21] are all logic low. Is that what you want?

No, from 37 to 33 must be set as inputs, i have the following definition on the RTL file:

Your inputs look ok. I’m not talking about the gpio settings. CVC is saying that

io_out[31:21]

are stuck at low. Does that seem strange to you? Should I look into the reason?

No, it's ok, the output I don't use were set to 0, trying to set all inputs/outputs with specific values.

So the only output you use is

io_out[32]

?

No, the GPIO[31:21] are the output of the FPGA (output for reconfigurable logic) and the GPIO 32 is output control signal of the FPGA. Just now, the precheck finished and all check passed, but no im orry about the output signals that you mention. At RTL the singnals looks well conected but i dont no if the reports tell you another thing.

It’s not a problem with precheck, but might be a problem with gate level verilog simulation. Are you able to run simulations on the gate level verilog?

Looking the GL verilog files the GPIO ports who are used as a output of the FPGA are conected to a cell "gf180mcu_fd_sc_mcu7t5v0__buf_8" while those ports that are set with 0 are conected to a "gf180mcu_fd_sc_mcu7t5v0__tiel" cell. Yes its possible to make a GL simultion but its a complex task and ill take a some days to do it, mainly due to the complex task to send the bitstream file correctly and simlate the whole reconfiguration of the FPGA, additionally, some times that big simulation only can be done with formal tools like QuestaSim due to the complexity of an FPGA. I will working on it, thnks for your help and your support.

I’ve traced the

io_out[21]

signal back to

cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_

which is tied low in

cbx_1__0_

.

vss->bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_ at Xcbx_1__0__87(gf180mcu_fd_sc_mcu7t5v0__tiel) in cbx_1__0_.

bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_ is output from Xcbx_2__0_ in user_project_wrapper as cbx_1__0__1_bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_.
This is connected to top_width_0_height_0_subtile_0__pin_outpad_0_ of grid_io_bottom_2__0_ an instance of grid_io_bottom.

In grid_io_bottom, top_width_0_height_0_subtile_0__pin_outpad_0_ is buffered at Xinput3 to give net3.
net3 is buffered to give gfpga_pad_GPIO_PAD[0] at X_15_.

gfpga_pad_GPIO_PAD[0] is output as net22 in user_project_wrapper.

net22 is buffered at Xoutput22 to give io_out[21].

I suspect that

bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_

is defined as an output of

cbx_1__0_

, but is not driven. Can you verify the spelling and that the net is actually driven in

verilog/rtl/cbx_1__0_.v

?