Hi everyone! I'm trying to layout the SARLOGIC component for a SARADC in magic, which involves two chains of flip flops feeding into eachother. I believe everything is wired correctly, however I keep getting these no matching net errors specifically for transistors within the DFF standard cell components. Here are a few files containing the comp error log as well as schematic and layout spice files. If anyone has an idea as to what I can do to fix this I'd very much appreciate it thank you! @Tim Edwards

Looks like

q3

and

q4

are shorted to an internal net in

sky130_fd_sc_hd__dfrbp_1

. The pin mismatch that you see in

sky130_fd_sc_hd__dfrbp_1

and

sky130_fd_sc_hd__dfbbp_1

are caused by shorts to non-port nets in those standard cells. Highlighting the nets in klayout might help locate the problem.

I am using Magic instead of Klayout, but I attempted to label some nets. Could I ask how you determined that q3 and q4 are shorted? It would really help me improve at understanding the skywater error messages. Thank you!

q3

and

q4

don’t appear on the layout side of the compare report. But maybe that was a bad guess.

q5

has different connection counts. Layout

Net: q5                                    
  sky130_fd_pr__pfet_01v8_hvt/2 = 2                                                   
  sky130_fd_pr__nfet_01v8/2 = 2                                                       
  sky130_fd_pr__pfet_01v8_hvt/(1|3) = 1                                               
  sky130_fd_pr__nfet_01v8/(1|3) = 1

Source

Net: q5                                    
  sky130_fd_pr__pfet_01v8_hvt/(1|3) = 1    
  sky130_fd_pr__nfet_01v8/(1|3) = 1        
  sky130_fd_pr__nfet_01v8/2 = 1            
  sky130_fd_pr__pfet_01v8_hvt/2 = 1