i ran a precheck on my design and it failed on LVS errors, ```ERROR LVS FAILED, stat=1, see /home/kr...

Kristaps Jurkans

12/09/2023, 11:26 AM

i ran a precheck on my design and it failed on LVS errors,

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ERROR LVS FAILED, stat=1, see /home/kris/repos/diy-ic/lincoln-gfmpw-1d/precheck_results/09_DEC_2023___02_03_14/logs/LVS_check.log
{{LVS CHECK FAILED}} The design, user_project_wrapper, has LVS violations.

looking into the log it states:

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Soft check result:
Final result: 
Circuits match uniquely.
.

LVS result:
Final result: 
Circuits match uniquely.
.
LVS Done.
Warning: device level LVS may be incomplete due to 6 unflattened cell(s): see /home/kris/repos/diy-ic/lincoln-gfmpw-1d/precheck_results/09_DEC_2023___02_03_14/outputs/reports/lvs.unflattened
LVS problem: check the following files
/home/kris/repos/diy-ic/lincoln-gfmpw-1d/precheck_results/09_DEC_2023___02_03_14/logs/ext.log
/home/kris/repos/diy-ic/lincoln-gfmpw-1d/precheck_results/09_DEC_2023___02_03_14/logs/lvs.log
/home/kris/repos/diy-ic/lincoln-gfmpw-1d/precheck_results/09_DEC_2023___02_03_14/outputs/reports/lvs.report

CVC result:
CVC: Total:                 0

Runtime: 0:00:58 (hh:mm:ss)

WARNING: possible errors SOFT 0 LVS 5 CVC 0

and looking at the unflattened lvs log shows me:

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ram_5x32 is a black box in the source
titan is a black box in the source
manchester_baby is a black box in the source
ram_5x32 contains no devices
titan contains no devices
manchester_baby contains no devices

is this something i could safely ignore?

Mitch Bailey

12/09/2023, 1:50 PM

Try adding the gl verilog for

ram_5x32

titan

and

manchester_baby

LVS_VERILOG_FILES

lvs/user_project_wrapper/lvs_config.json

. Be sure to put the child modules before their parents.

Kristaps Jurkans

12/09/2023, 2:27 PM

it seems to have helped, although i'm not getting errors like these:

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Warning:  Cell INSTRUCTION_WIDTH-1 has no pins
Creating placeholder cell definition for module INSTRUCTION_WIDTH-1.
Note:  Implicit pin (no pins) in instance : of INSTRUCTION_WIDTH-1 in cell core_interface
Expected to find instance pin block but got "input"
Expected to find end of instance but got "wire"
line number 19 = '    input wire [ADDRESS_WIDTH-1:0] address_i,'

could this be due to the files being systemverilog and not regular verilog?

LVS_check.log

Mitch Bailey

12/09/2023, 2:29 PM

Try adding the gl verilog

Kristaps Jurkans

12/09/2023, 2:30 PM

ohhh my bad, lemme try that

Kristaps Jurkans

12/09/2023, 2:39 PM

okay, got no errors! thank you for your help 🙌

👍 1

Anton Maurovic

12/10/2023, 9:33 AM

Unrelated @Kristaps Jurkans, did you manage to sort out your hold violations we were discussing in the GFMPW-1 support session?

Kristaps Jurkans

12/10/2023, 10:45 AM

@Anton Maurovic yeah, kinda. i managed to fix it for the macro i was initially having problems with, since it was just a misconfiguration issue that i had overlooked. but i ran into more violations whilst trying to harden a completely different macro, it was related to

wb_addr

and

wb_clk

and honestly i wasn't too sure how to solve those

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