CAN ANY ONE HELP?
# general
m
CAN ANY ONE HELP?
v
Use
openroad -gui
and load your .odb file and search for pins. Syntax
Copy code
get_pins [-hierarchical] [-hsc separator] [-quiet] [-filter expr] [-regexp]
   [-nocase] [-of_objects objects] patterns
m
Its not working. The pin it shows is different. When I checked with [get_pins *] command, in OpenLane, It give some kind of numbered pins [ex pin_01234_x].
The name of pins are not same as define in .v file.
I am facing this error while defining {generated_clock} in SDC file, where we have assign the generated clock on the PIN. That pins not accessible.
v
share the odb file and pin name trying to search, along with command you're trying
m
set PD_SCL_period 1000.0 set AD_OSC_period 333 create_clock -name PD_SCL -period $PD_SCL_period [get_ports PD_SCL] -waveform {0 500} create_clock -name AD_OSC -period $AD_OSC_period [get_ports AD_OSC] -waveform {0 166} create_generated_clock -name AD_OSC_div2_clk -source AD_OSC [get_pins control/count_reg_reg_0_/Q] -divide_by 2 -master_clock AD_OSC -add create_generated_clock -name AD_OSC_div1024_clk -source AD_OSC [get_pins control/count_reg_reg_9_/Q] -divide_by 1000 -master_clock AD_OSC -addQ
This is part of SDC.
When I try to do synthesis, it gives me an error that control/count_reg_reg_0_/Q pin is not available.
I am doing synthesis.
v
share the netlist file
m
can you give email address?
a
@Munjani Jayesh it is highly likely that your hierarchy is being flattened. You need to find the flat name to constrain the clock on. Or, you need to turn off synthesis flattening for that module in Yosys.
m
image.png
I am getting pins name like this.