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Hi <@U017X0NM2E7>! I've got a problem with OEB in precheck. My design contains efuse cells, which ar...
# gf180mcu
e
Hi @Mitch Bailey! I've got a problem with OEB in precheck. My design contains efuse cells, which are extracted, but efuse model is not present in resulting CDL. OEB seems not to include SPICE files from lvs_config.json, so I see no way to add this model to CDL. Is there a way to workaround this problem? Log:
Copy code
CVC: Reading device model settings...
CVC: Reading power settings...
CVC: Parsing netlist /mnt/users_data/jobs/egorxe/Ophelia_eFPGA_rerun/fbdb3f4a-4990-4ede-bfcd-db632f0d30b5/tmp/ext/user_project_wrapper.cdl.gz

Cdl fixed data size 6258664
Usage CDL: Time: 1  Memory: 102760  I/O: 56  Swap: 0
CVC: Counting and linking...
Fatal error:could not find subcircuit: X6(efuse) in efuse_array
m
I’ll probably need to update the CVC/OEB tech files. Can you share your 
<tag>/tmp/ext/user_project_wrapper.gds.spice
file?
e
Sure. Thanks for your help!
user_project_wrapper.gds.spice.gz
m
With your local precheck, can you try replacing 
checks/be_checks/tech/gf180mcuD/cvc.models
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D np_6p0
D pn_6p0 
D diode_nd2ps_06v0
D diode_pd2nw_06v0

D condiode

R ppolyf_u_1k_6p0 R=r_length/r_width*50
R ppolyf_u R=r_length/r_width*50
R efuse R=100

MN nfet_06v0 Vth=0.4
MN nfet_06v0_dss Vth=0.4
MP pfet_06v0 Vth=-0.4
MP pfet_06v0_dss Vth=-0.4
MN nmos_6p0 Vth=0.4
MP pmos_6p0 Vth=-0.4
MN nmos_3p3 Vth=0.3
MP pmos_3p3 Vth=-0.3

C mim_2p0fF

C cap_mim_2f0_m4m5_noshield
C cap_nmos_06v0
and 
checks/be_checks/tech/gf180mcuD/spi2cdl
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#! /bin/bash

awk '
/^X.*pr__diode.*=/ {
        print "D" $0;
        next;
}
/^X.*pr__special_[^ _]*fet.*=/ || /^X.*pr__.fet.*=/ || /^X.*pr__esd_.fet.*=/ || /^X.*[np]fet_[0-9]*v[0-9].*=/ || /^X.*[np]mos_[36]p[03]/ {
        print "M" $0;
        next;
}
/^X.*pr__pnp_.*=/ {
        print "Q" $0;
        next;
}
/^X.*pr__cap_mim_.*=/ || /^X.*mim_2p0fF.*=/ || /^X.*cap_mim_2f0_m4m5/ || /^X.*cap_nmos/ {
        print "C" $0;
        next;
}
/^X.*pr__cap_var.*=/ {
        bulk = $4;
        $4 = "";
        print "C" $0, "$SUB=" bulk;
        next;
}
/^X.*pr__res_.*=/ || /^X.*ppolyf_u/ {
        bulk = $4;
        $4 = "";
        print "R" $0, "$SUB=" bulk;
        next;
}
/^X.*sky130_fd_pr__reram_reram_cell.*=/ {
        print "R" $0;
        next;
}
/^X.* efuse *$/ {
        print "R" $0;
        next;
}
/^R/ && NF == 4 && $4 == "0.000000" {
        $4 = "short " $4;
}
 {
        print $0;
}' $1
e
OEB check passes this way. Please notify me when platform precheck will be updated. Thank you!
👍 1
m
Are you getting any other errors in precheck? multi-pdn?
e
In local precheck I have only LVS failing due to "device level LVS may be incomplete" which is OK as far as I understand. On my first platform precheck run I had multi-PDN error along with OEB error because I did not add config.json file to repo. It was easy to fix obviously so now I'm waiting for your confirmation of OEB fix to run new platform preckeck attempt.
m
We’re having an online meeting now. @jeffdi has decided to override the pre-check. You should be able to proceed with the tapeout.
e
Will it be possible for me to update GDS, or current should be the final one?
m
Jeff would need to override if you updated anything.
e
Ok, so I'll perform a tapeout now and in case of update write to you and Jeff asking to approve if possible. Thanks again!
👍 1
Hello @jeffdi and @Mitch Bailey! I've updated my design with slightly improved and much better tested version. Precheck fails as before on OEB check due to the lack of efuse model, precheck ID a2dc08bb-669f-4344-b4ee-bc397b89b076. If possible please run the tapeout override again to get updated version. Among other improvements latest version was tested with device level LVS without ignores on efuse cells. It takes 8 hours on my machine to complete such LVS because partial netlist flattening is required to get a match in netgen. I could provide local precheck logs if required or add them to repo.
j
@Egor Lukyanchenko just submitted
👍 2
e
Thanks a lot, Jeff!
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