To use the updated tag, make sure you don’t have any environment overrides

env | grep COMMIT
env | grep TAG
echo $PDK

and then

curl <https://raw.githubusercontent.com/efabless/caravel_user_project/gf180mcu/Makefile> > Makefile
make setup

Be warned that the CVC/OEB check will fail if there are 3v devices. If you really need 3v devices, I can provide a local patch. Also be warned that the sram’s in the pdk will extract as 3v devices unless you provide instructions for flattening. In the

lvs/user_project_wrapper/lvs_config.json

file, add

"SRAM_MACRO": "sram256x8m8wm1",
        "INCLUDE_CONFIGS": [
                "$LVS_ROOT/tech/$PDK/lvs_config.sram.json"
        ],

I tried to run CocoTB tests (gpio_test) with a new repo created from the provided new tag, however, I still had to do this: 1. Updating Makefile as indicated here, the Makefile that comes with the repo is outdated 2. Manually update the design_info.yaml in verilog/dv/cocotb setting the values to the directories where PDK, Caravel and the user's repo are, this made me realize MGMT Core Wrapper seems to require a manual installation 3. Clone caravel_mgmt_soc_gf180mcu repo and update the remaining value of previous step 4. There seem to be a naming issue with power pins so I had to modify the file caravel/verilog/rtl/caravel_core.v line 384 and 385 to vccd1 and vssd1 respectively I am sharing this in case it results useful for someone and to see if anyone sees I'm doing something I shouldn't, but now I'm able to run the tests and it passes

Where is this file lvs_config.sram.json located? I could not find it @Mitch Bailey

In precheck,

LVS_ROOT

is defined as

$PRECHECK_ROOT/checks/be_checks

. The default location for

PRECHECK_ROOT

is

$HOME/mpw_precheck

Please be user to use the

gfmpw-1d

version of the

caravel_user_project/Makefile

.

If I use SRAMs in my design, will they function properly with a 5V supply? I understand the GF180MCU supports 1.8V, 3.3V and 5V SRAMS, how do I know which one is used?

I have not heard that gf180mcu supports 1.8V. The I/O ring is 5V and only one voltage is used. Are you using the srams from the PDK? If so, I believe they are 5V.

This is where I obtained the information: https://gf180mcu-pdk.readthedocs.io/en/latest/IPs/SRAM/gf180mcu_fd_ip_sram/cells/gf180mcu_[…]sram512x8m8wm1/gf180mcu_fd_ip_sram__sram512x8m8wm1.html Yes I am using SRAMs from the PDK. However since both the OEB and LVS prechecks fail due to missing 3v3 modules (related to the SRAM modules), I was wondering whether they are designed to be operated with 3.3V.

Actually, the srams are using 5V devices but the implant layers are on a different hierarchy so they are incorrectly extracted as 3.3V devices. The solution is to add the following lines at the beginning of your

lvs/user_project_wrapper/lvs_config.json

file.

"SRAM_MACRO": "sram512x8m8wm1",
        "INCLUDE_CONFIGS": [
                "$LVS_ROOT/tech/$PDK/lvs_config.sram.json"
        ],

This clears up why this patch is needed, thanks for the clarification! I have run into some problems however. After applying the patch OEB and LVS checks still failed because the SRAM_MACRO "sram512x8m8wm1.gds" was not found. I looked into the pdk and found that the file name was set to "gf180mcu_fd_ip_sram__sram512x8m8wm1" and after chaning it LVS passed but OEB is still failing. I'm getting the following error:

ERROR: Could not find /home/luke/work/asic/caravel_user_project-1d/precheck_results/08_DEC_2023___10_53_19/tmp/cvc.power.gf180mcu_fd_ip_sram__sram512x8m8wm1

The tmp directory is non-existing.

Can you share your full

lvs/user_project_wrapper/lvs_config.json

file?

Here it is:

Actually, the srams are using 5V devices but the implant layers are on a different hierarchy so they are incorrectly extracted as 3.3V devices. The solution is to add the following lines at the beginning of your

lvs/user_project_wrapper/lvs_config.json

file.

The order is important.

Placing it at the beginning, with `"SRAM_MACRO": "sram512x8m8wm1"`solves the issue and OEB check passes. LVS does not complete successfully, showing 5 errors. I am not sure why as the

lvs.log

shows no errors, and all lvs checks carried out by openlane are successfull

The LVS result is ok when all your macros are black-boxed, but the precheck LVS is trying to do a full device level check. There are missing verilog blocks

Warning: device level LVS may be incomplete due to 16 unflattened cell(s): see /home/luke/work/asic/caravel_user_project-1d/precheck_results/08_DEC_2023___18_58_06/outputs/reports/lvs.unflattened

You can check

lvs.unflattened

and add those to

LVS_VERILOG_FILES

in

lvs_config.json

. Be sure to list the lower level verilog modules before the parent modules.

Including all macros resolved the warning. I still have something wrong with the pre-check LVS tough, the check of all macros is ok. The LVS for the

user_project_wrapper

file is giving

DEVICE mismatches

and then listing all four SRAM instances I have in my design. It seems that there is some issue with the names. I've attached the report: line 6632 states the netlist mismatch, while line 7264 states the device mismatch. It seems that multiple instances of the same module, connected with subsets of the same signal is the issue ...

Can you share your

lvs_config.json

file(s)?

Here it is. Please ignore previous report.

Be sure to list the lower level verilog modules before the parent modules.

The config file currently has the top level first.

LVS check completes successfully. Issues with the SRAM model still persist. In my design I have a wrapper around the blackbox model for

gf180mcu_fd_ip_sram__sram512x8m8wm1.v

which I copied from the PDK into my design directory. When I harden my wrapper design, I only get a a gate level verilog file for the wrapper.

lvs.unflattened

lists two unflattened devices:

gf180mcu_fd_ip_sram__sram512x8m8wm1 is a black box in the source
gf180mcu_fd_ip_sram__sram512x8m8wm1 contains no devices

Sorry about that. Try

"SRAM_MACRO": "gf180mcu_fd_ip_sram__sram512x8m8wm1",

That does it, all checks passed! Thank you so much David, really appreciate your help with this.