"Explore an opportunity in our RISC-V design and verification course. This program offers a hands-on journey through the design of an RV32 processor. Starting with a single-cycle model, we'll advance to a multi-cycle and then a pipelined architecture, incorporating custom extensions. Practical learning is a key focus, as we'll use Verilog for design and testbench development. The course also includes an in-depth review of the ibex open-source core by lowRISC, a Google initiative. Participants will gain insights into architectural and microarchitectural concepts, covering branch prediction, superscalar design, out-of-order execution, and multi-core/multi-threading technologies. This is an ideal course for those looking to deepen their understanding of modern processor design." The crash course is this weekend. https://vlsideepdive.com/risc-v-microarchitecture-rtl-design-and-verification/