Hi, @Mitch Bailey I am running local pre-checks on my design. I am getting error in xor checks. I am using all the default values for PDN generation and IO pins as per the tag gfmpw-1b and am building the design directly in the wrapper not importing it as a macro. I wanted to ask if reducing the pdn spacing will make a difference in the said issue. Also if I reduce he core area and keep the die area same will it make the xor checks likely to pass. Is changing the core area likely to cause issue in tapeout job?

@Abdul Moiz Sheikh Reducing the pdn spacing should not make a difference in the xor check. The power rail layers are removed before comparison. I’m not sure about the core area/die area change, but I’m inclined to believe there won’t be a problem. Let me no if you run into problems.