Hello, I am getting LVS issues that seems related to parallel merging on tap, decap, fill, and diode cells.:

Class user_project_wrapper (0):  Merged 554701 parallel devices.
Class user_project_wrapper (1):  Merged 603433 parallel devices.

Subcircuit summary:
Circuit 1: user_project_wrapper            |Circuit 2: user_project_wrapper            
-------------------------------------------|-------------------------------------------
...   
sky130_fd_sc_hd__tapvpwrvgnd_1 (77463->171 |sky130_fd_sc_hd__tapvpwrvgnd_1 (77463->1)  
sky130_ef_sc_hd__decap_12 (246728->1717)   |sky130_ef_sc_hd__decap_12 (246728->1) **Mi 
sky130_fd_sc_hd__diode_2 (59859->45770)    |sky130_fd_sc_hd__diode_2 (59859->10468) ** 
sky130_fd_sc_hd__decap_3 (22133->1717)     |sky130_fd_sc_hd__decap_3 (22133->1) **Mism 
sky130_fd_sc_hd__decap_6 (52682->1717)     |sky130_fd_sc_hd__decap_6 (52682->1) **Mism 
sky130_fd_sc_hd__fill_1 (71133->1717)      |sky130_fd_sc_hd__fill_1 (71133->1) **Misma 
sky130_fd_sc_hd__fill_2 (49934->1510)      |sky130_fd_sc_hd__fill_2 (49934->1) **Misma 
sky130_fd_sc_hd__decap_8 (19133->1709)     |sky130_fd_sc_hd__decap_8 (19133->1) **Mism 
...   
sky130_fd_sc_hd__decap_4 (14844->1634)     |sky130_fd_sc_hd__decap_4 (14844->1) **Mism

In this discussion, @Tim Edwards explained in regard to decap cell mismatches after parallelization: "The main thing is that the decap cells in the layout have not been combined in parallel; you should end up basically with one decap cell of each type on each side. Since decaps connect only to power and ground, you need to figure out what's going on with the power and ground in your layout netlist." Looking at the GDS, the power grid is connected to my SRAM macros, but it does not seem to be connected to anything else below layer M4, so I think the cells are not being connected to the power grid. The right side seems to be merging down to a single instance for each of these modules, but the left side is reducing to a much larger number for each cell type, probably groups that are tied together in parallel at layers M3 or below. Parallel devices are being merged, just not all of them as expected.

@Peter Herrmann I’d say your analysis of the LVS results is spot on. I downloaded the gds, but couldn’t see any obvious errors. I’ll look again when I’m awake.

LOL get some sleep