So I then included

TOP_digital.v

(the gate level which Openlane had previously generated) and its caused it to fail, but I think its just because of a mismatch between bus/pin ordering somewhere in our verilog netlists? The user_project_wrapper comparison is complaining about mismatched pins, however all of these are present in both left and right columns, just in a different order. All the pins its unhappy about are all the ones we used in

TOP_digital

.

@Ellen Wood Can you share the full

lvs.report

? and maybe your

lvs_config.json

file? If you’re using verilog instances calling spice subckts, you do need to be careful of the spice port bus order.

Hi @Mitch Bailey, I have shared them in my message (and replies) immediately below this one.. apologies, not sure where to put all my messages on the slack!