Hugo Dias
10/28/2023, 1:45 PMMitch Bailey
10/28/2023, 3:01 PMconfig.json
file for user_analog_project_wrapper
. I imagine you’ll need FP_PDN_MACRO_HOOKS
, SYNTH_USE_PG_PINS_DEFINES
, etc.steven darker
10/28/2023, 4:29 PMHugo Dias
10/28/2023, 9:21 PMHugo Dias
10/28/2023, 9:37 PM{
"DESIGN_NAME": "sr",
"VERILOG_FILES": "dir::src/*.v",
"CLOCK_PORT": "sclk",
"CLOCK_PERIOD": 10.0,
"DESIGN_IS_CORE": true,
"FP_PIN_ORDER_CFG": "dir::pin_order.cfg"
}
Mitch Bailey
10/29/2023, 6:39 PMsr
circuit a hard macro that you want to place in user_analog_project_wrapper
with openlane or do you intend to manually place and route the user_analog_project_wrapper
block?Hugo Dias
10/31/2023, 1:27 PMMitch Bailey
10/31/2023, 1:47 PMuser_analog_project_wrapper
power ring.