Hello, I am failing the MPW precheck for XOR errors, it appears that the pins for my user_project_wrapper are outside the core area by 4.8um.

{{STEP UPDATE}} Executing Check 4 of 12: XOR
{{XOR CHECK UPDATE}} Total XOR differences: 1190, for more details view /home/prherrma/runners/r0/_work/tapeout-ci-2311/tapeout-ci-2311/mpw_precheck_result/outputs/user_project_wrapper.xor.gds
{{XOR CHECK FAILED}} The GDS file has non-conforming geometries.

I used the caravel reference project to set up the repo, which had the following lines:

"UNIT": 2.4,
    "FP_IO_VEXTEND": "expr::2 * $UNIT",
    "FP_IO_HEXTEND": "expr::2 * $UNIT",
    "FP_IO_VLENGTH": "expr::$UNIT",
    "FP_IO_HLENGTH": "expr::$UNIT",

This appears to set the pins to outside the die area by 4.8um, which is what I am seeing, but that project is not failing XOR checks. Can anyone see what I am doing wrong? suspect the problem is with my

config.json

(attached), but if not my repo is here.

Your pin locations do not match the caravel_core. They will not connect as expected. The XOR check only checks the halo, that’s why you’re only seeing 4.8um. Looking at the layout, I think openroad/lane tries to space the pins evenly across each side centered in the middle. The pitch on your pins is just a little less than on the default project, but I can’t figure out why yet.

Thanks Mitch. Sorry for the late reply, I spotted that and hadn't updated the thread since I haven't gotten the flow to MPW precheck yet with that addition to confirm the fix.

Hi @Peter Herrmann, a few questions, did you have any problems with the System Verilog (SV) files?, did you use any constraint or make any changes to synthesize your project with SV?

Hey @Emilio Baungarten, for yosys to read a file as SV, you need to add the -sv flag; I added this to verilog/includes/includes.rtl.caravel_user_project and that worked.

Thanks, that's really helpful to know.