Hi, I am trying to use the wishbone bus to communicate between the user module and RISC V processor. I was wondering about the behavior of the processor when a request is not completed immediately (o_wb_ack is not immediately high). Are writes/reads to the user area address blocking or nonblocking?

All wishbone accesses will block the CPU until the peripheral signals

o_wb_ack

. The peripheral can claim as many clock cycles as it needs to complete the read or write.

Thank you!

Try the wb simulation in verilog/dv/