Hello, I've identified an issue while attempting LVS using Netgen. I've noticed that the pin orders of the standard cells being used in the .spice files extracted from Xschem and Magic are different from each other. Do you know why this issue has occurred? I'm using the standard cells from SkyWater130n.

@정진형학부생 If the ports are labeled, pin order shouldn’t matter. Can you share your extracted spice and the spice generated from the schematic? When you generate the schematic spice, be sure

Simulation

->

LVS netlist: Top level is a .subckt

is selected.

I used the following files: The file extracted from Magic is named "magic_origin.spice," and the file extracted from Xschem is named "xschem.spice." I used "magic.spice" and "xschem.spice" when running LVS (with the .subckt removed). I have confirmed that "LVS netlist: Top level is a .subckt" is selected in Xschem.

@정진형학부생: You might claim that the "Top level is a .subckt" is checked, but the netlist you posted above (xschem.spice) clearly didn't have that option checked when it was created. Nevertheless, the issue highlighted in your first post is that you need to include the netlist library of the standard cells. Otherwise, the schematic-captured netlist does not contain any information about the contents of the standard cells, or their pins. The file that needs to be included is (assuming a PDK in

$PDK_ROOT

):

$PDK_ROOT/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice

.

The file $PDK_ROOT/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice already exists at that location. Is there any syntax that needs to be added to the .spice file? And it seems that xschem.spice was my mistake. I sent a file with commented out .subckt for running LVS. The original file is here. (I commented out the .subckt since it problem the contain device is 0.)

@정진형학부생 Here’s a couple suggestions: 1. Save the schematic as

hgu_sarlogic_8bit_logic.sch

and re-netlist. 2. Make sure your layout has ports that match the schematic. See this thread for information about making ports in magic. 3. As @Tim Edwards mentioned, be sure to include the spice library for the standard cells. You can do this in xschem by adding a

devices/code.sym

symbol and setting the value to

name=SPICE_INCLUDE
only_toplevel=true
format="

.include $::SKYWATER_STDCELLS/sky130_fd_sc_hd.spice


"

@정진형학부생: The best approach for running LVS on a schematic-captured netlist is to have the subcircuit inside a testbench. The testbench should instantiate the circuit and include the necessary PDK netlists. That keeps things like the ".include" statement out of the subcircuit netlist. You can run netgen and specify the top-level testbench netlist as the input file but specify the subcircuit as the topmost cell to be compared. Removing the ".subckt" line is not a solution. At best, it just prevents netgen from making a comparison all the way out to the pins of the subcircuit, but that risks hiding real errors that may be in the circuit schematic or layout.

Thank you to everyone who helped. I confirmed there was an issue during the process of running LVS. I thought that removing the ".subckt" was the easiest way, but it turns out that it's not the right approach. When I kept the ".subckt" and ran LVS, I encountered a dummy problem, but as you suggested, adding ".include" resolved this issue. Thank you for your attention to my problem.