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`VSUBS` showing up out of nowhere
# analog-design
a
VSUBS
showing up out of nowhere
Searching through threads here, I've seen that when 
VSUBS
shows up in the netlist extracted (for 
lvs
) from Magic, that means that we didn't connect up the substrate... Well, the thing in our case is the following: 1. we have 5 subcells (one of them a simple opamp), each designed on its own, each carefully and thoroughly checked against DRC and LVS 2. we have put those 5 subcells in a top cell magic file and routed them together. 3. we connected all the grounds together in Magic layout just the same as in Xschem top cell schematic 4. during extraction of independent subcells we never saw any report of 
VSUBS
5. when doing
Copy code
extract all
ext2spice lvs
ext2spice
on the top cell, we get a spice netlist that puts 
VSUBS
instead of the gnd node in the opamp (called 
ground
, we didn't use global nodes)... When we do LVS, for 4 subcells we get:
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Flattening unmatched subcell sky130_fd_pr__res_xhigh_po_0p69_XZX24Q in circuit dac_cell2 (1)(4 instances)
Flattening unmatched subcell sky130_fd_pr__pfet_g5v0d10v5_FGUWVM#1 in circuit dac_cell2 (1)(1 instance)
Flattening unmatched subcell sky130_fd_pr__pfet_g5v0d10v5_FGK6VM in circuit dac_cell2 (1)(3 instances)

Class dac_cell2 (0):  Merged 2 parallel devices.
Class dac_cell2 (0):  Merged 1 series devices.
Class dac_cell2 (1):  Merged 2 parallel devices.
Class dac_cell2 (1):  Merged 1 series devices.
Subcircuit summary:
Circuit 1: dac_cell2                       |Circuit 2: dac_cell2                       
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_g5v0d10v5 (4)           |sky130_fd_pr__pfet_g5v0d10v5 (4)           
sky130_fd_pr__res_xhigh_po_0p69 (4->1)     |sky130_fd_pr__res_xhigh_po_0p69 (4->1)     
Number of devices: 5                       |Number of devices: 5                       
Number of nets: 9                          |Number of nets: 9                          
---------------------------------------------------------------------------------------
Resolving symmetries by property value.
Resolving symmetries by pin name.
Netlists match uniquely.

Subcircuit pins:
Circuit 1: dac_cell2                       |Circuit 2: dac_cell2                       
-------------------------------------------|-------------------------------------------
vgnd                                       |vgnd                                       
vbias                                      |vbias                                      
vsw                                        |vsw                                        
iout_n                                     |iout_n                                     
iout                                       |iout                                       
vsup                                       |vsup                                       
iref                                       |iref                                       
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes dac_cell2 and dac_cell2 are equivalent.
but for the subcell 5, the opamp we get:
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Circuit 1: miel21_opamp                    |Circuit 2: miel21_opamp                    
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_g5v0d10v5 (3)           |sky130_fd_pr__pfet_g5v0d10v5 (26->3)       
sky130_fd_pr__nfet_g5v0d10v5 (5)           |sky130_fd_pr__nfet_g5v0d10v5 (14->5)       
sky130_fd_pr__res_xhigh_po_0p69 (3->1)     |sky130_fd_pr__res_xhigh_po_0p69 (3->1)     
sky130_fd_pr__cap_mim_m3_1 (1)             |sky130_fd_pr__cap_mim_m3_1 (1)             
Number of devices: 10                      |Number of devices: 10                      
Number of nets: 9                          |Number of nets: 9                          
---------------------------------------------------------------------------------------
Netlists match uniquely.

Subcircuit pins:
Circuit 1: miel21_opamp                    |Circuit 2: miel21_opamp                    
-------------------------------------------|-------------------------------------------
ground                                     |VSUBS **Mismatch**                         
inNeg                                      |inNeg                                      
inPos                                      |inPos                                      
outSingle                                  |outSingle                                  
power                                      |power                                      
---------------------------------------------------------------------------------------
Cell pin lists for miel21_opamp and miel21_opamp altered to match.
Device classes miel21_opamp and miel21_opamp are equivalent.
and then (omitting quite a bit of lines)
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Circuit contains 12 nets, and 2 disconnected pins.

Circuit 1 contains 8 devices, Circuit 2 contains 8 devices.
Circuit 1 contains 12 nets,    Circuit 2 contains 12 nets.


Final result: 
Top level cell failed pin matching.

Logging to file "comp.out" disabled
LVS Done.
Again, note that individual LVS check for the opamp passes without any issues, circuits and netlists equivalent. And yet, here netgen shows 
Mismatch
for that very same circuit. @Tim Edwards do you have an idea, maybe?
Here is the complete 
comp.out
comp.out
comp.out
t
Determining where the substrate is in every cell gets rather complicated. In this case, the top level cell (first extracted by magic independently of its subcells) has no substrate connection itself (all the connections are in subcells), so the top level cell gets extracted with a 
VSUBS
substrate node that is not connected to ground. Then it is hard for magic to figure out that all the subcell substrates connect together, connect to 
VSUBS
and thereby connect 
VSUBS
back to 
ground
through the subcells. The easiest thing to do is just to draw a single substrate contact (
psc
on 
psd
) on the ground net in the top level cell. That will tie 
ground
to the substrate in the top level cell and avoid the extraction problem.
a
Hi @Tim Edwards, thanks! So, something like this:
I seem to be missing a layer... as with the above, I still get VSUBS in the extracted netlist, even though the m1 to the right goes directly to the VGND pin of the top cell.
t
That looks right. I would have thought that would solve the issue. Feel free to share the layout with me and I'll take a look at it.
a
That archive doesn't have the contact I just created above, I packed it before the attempt...
t
Well, that gives me something to debug, anyway. . . : ) So the issue is that the same issue repeats hierarchically at the level of 
miel21_opamp
. That cell also has substrate connections only within subcells. So if you draw yet another substrate contact inside 
miel21_opamp
that is connected to net 
ground
, that will fix the issue (I confirmed it). It's definitely an error in magic that it extracts the ground net of 
miel21_opamp
as 
VSUBS
and not as 
ground
, and the pin 
ground
vanishes from the netlist. But if you use the workaround, then I don't have to treat the error as desperately needing attention.
a
Of course, gladly, right away. Let me confirm in a few minutes
Ok, I've updated the layout of 
miel21_opamp
, so just wandering now for the love of philosophy - what's the proper way of "refreshing" it in the top cell (and not close/open Magic)?
t
flush miel21_opamp
would do it.
a
yes, 
VSUBS
is definitely gone, thank you! It seems there's something messed up with the netlist coming out of 
dac_cell3
, so we'll take a look there. However, it is reporting another strange thing:
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Subcircuit pins:
Circuit 1: dac_top_cell                    |Circuit 2: dac_top_cell
-------------------------------------------|-------------------------------------------
out                                        |out
vbias07                                    |(no matching pin)
in3                                        |in3
in1                                        |in1
vbias18                                    |vbias18
in4                                        |in4
in2                                        |in2
vgnd                                       |vgnd
vsup                                       |(no matching pin)
(no matching pin)                          |vbias07
(no matching pin)                          |vsup
vbias07                                    |(no matching pin)
vsup                                       |(no matching pin)
---------------------------------------------------------------------------------------
Cell pin lists for dac_top_cell and dac_top_cell altered to match.
Device classes dac_top_cell and dac_top_cell are equivalent.

Final result: Top level cell failed pin matching.
There obviously is 
vbias07
in both circuits, so... Is this common behavior from 
netgen
when there is a misconnection or again something we need to tackle with a workaround?
Also, how dangerous is this "altered to match" notification?
t
@Aleksandar Pajkanovic: Reviewing your layout, the answer in this case is that you have pins that are not on the layer of the net they are sitting on top of. "vbias07" is on metal1 but is sitting on a metal2 wire, so it is not connected. The same is true of "vsup". You can either move the labels to a metal1 wire on the same net, or you can select the label and run the command 
setlabel layer metal2
. Then you can erase the floating square of metal1 that used to be the label attachment area.
👍 1
a
So many dimensions to track issues :) thanks so much!
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