Another question is about Verilog-A and xschem. I don't know if there are open source digital simulators that also support Verilog-A. The ngspice SPICE simulator can simulate Verilog-A modules that are compiled into .osdi files and placed in a directory known by the simulator. A good example is the reram testbench also provided by xschem_sky130. Since the top level netlist is a regular SPICE netlist all I needed to do was to add the correct netlisting rule for the reram subcircuit. See the

tb_reram.sch

schematic. The

XR1

symbol is a subcircuit. The subcircuit instantiates the 'N... element that is a verilog-A primitive. This element calls a model that sets some parameter values and binds to a verilog-A module: •

XR1

--> subcircuit

sky130_fd_pr_reram__reram_cell

• subcircuit

sky130_fd_pr_reram__reram_cell

--> instantiates the '`N`' line with

sky130_fd_pr_reram__reram_model

model. • The

sky130_fd_pr_reram__reram_model

model sets some parameter values and binds to the

sky130_fd_pr_reram__reram_module

Verilog-A code. • The

sky130_fd_pr_reram__reram_module

code placed in a

<http://sky130_fd_pr_reram__reram_module.va|sky130_fd_pr_reram__reram_module.va>

file is compiled with

openvaf

and the generated .osdi file is placed in a place known by ngspice. • In the netlist there is a

pre_osdi

/path/to/sky130_fd_pr_reram__reram_module.osdi

that allows ngspice to link in the compiled module.

I need somebody to write down the detailed set of instructions on how to compile the OSDI model so that I can add the procedure to

open_pdks

and install the model into the PDK where it can be used automatically without requiring the end user to go to all the trouble of doing it themselves.

@Tim Edwards the process is very simple. • get

openvaf

. It is available precompiled for Linux and is extremely simple, it unpacks an

openvaf

executable

schippes@asus:~$ tar ztvf  Downloads/openvaf_23_5_0_linux_amd64.tar.gz 
-rwxr-xr-x 0/0       221692776 2023-05-16 13:51 openvaf

• Doing openvaf

<http://xxx.va|xxx.va>

generates

xxx.osdi

• Place these lines in the testbench

.control
   pre_osdi /path/to/xxx.osdi
.endc

• The boring part is the wrapping: VerilogA device --> subcircuit --> N line --> N model -->osdi module

@Stefan Schippers: The main point is to keep everything consistent so that the

/path/to/xxx.osdi

is always in, e.g.,

$PDK_PATH/libs.tech/ngspice/

or maybe

$PDK_PATH/libs.tech/osdi/

.