Many people ask if it is possible to simulate Verilog designs in xschem. In many cases a digital design is fully described in Verilog and there is a kind of "HDL to Layout" flow that does various steps, like: logic synthesis generating a RTL representation of the verilog code, mapping to technology-specific standard logic cells, timing analysis verification, clock tree generation, floorplanning, power and signal routing, various layout rule checks, antenna diodes insertion, spare cells, decaps insertion, filler cell insertion etc. (there are many more steps) In these flows a schematic view of the system is not even used. However in cases someone wants to draw the circuit in xschem, dividing the design into sub blocks, describing each block behavior with Verilog code and let xschem generate the structural netlist this is possible. There is an example of a mips cpu in the test circuits provided by xschem_sky130. The github page of the original design is here. See the video. @Ashutosh Kumar