rumaz
10/17/2023, 12:42 PMStefan Schippers
10/18/2023, 9:27 AMop
statement. Also ensure voltage sources have a defined time 0 value, like:
vxxx n1 n2 dc 5
or:
vxxx n1 n2 pwl 0 5 10n 5 11n 0
rumaz
10/18/2023, 9:42 AMStefan Schippers
10/18/2023, 11:28 AM1_nmos_vgs.sch
schematic? will do a test here.
Also click on the annotate op
symbol, press '`q`' and verify the raw file it is loading is the 1_nmos_vgs.raw
you have created in the simulation.
It looks like you are loading a raw file from another circuit or another simulation.rumaz
10/18/2023, 11:58 AMStefan Schippers
10/18/2023, 12:16 PMrumaz
10/18/2023, 12:29 PMStefan Schippers
10/18/2023, 1:05 PM