Hi, looking for a working config of using levelshifters sky130_fd_sc_hvl__lsbuflv2hv_1. LVS fails since LVPWR is not connected to vccd1

It does not pass LVS by itself, but it will pass in the parent level when placed and connected correctly. (this is netgen - don’t know about klayout).

Oh, interesting, how can I skip LVS in sub block?

With netgen, cells that don’t match are automatically flattened into the parent hierarchy.

Also in the gl verilog I don't have a connection to LVPWR, any ideas?

Not sure how to connect the level shifter power in verilog. For LVS, load the spice netlist for the standard cells from the PDK before running LVS. Replace

<*>

with your file/path names.

set layout [readnet spice <extracted netlist>]
set source [readnet spice <pdk root>/<pdk>/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice]
readnet spice /<pdk root>/<pdk>/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice $source
readnet verilog <verilog file> $source
lvs "$layout <layout top>" "$source <source top>" <setup file> <report file>