Our digital logic runs fine in the simulations, but we are getting the following error message while running openlane. Is there any way to see what the 167 yosys check errors are? In yosys-synthesis.log we can only see 1 error: "ABC: Error: The network is combinational"
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Mitch Bailey
10/10/2023, 2:26 PM
Just a guess, but maybe missing a signal defined as a clock?
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