Hi <@U0172QZ342D> Can please explain how did you controlled the following signals in your wishbone d...

ANKI REDDY SAI PRAVEEN

10/07/2023, 2:40 AM

Hi @Matt Venn Can please explain how did you controlled the following signals in your wishbone demo..?

input wb_rst_i,

input wbs_stb_i,

input wbs_cyc_i,

input wbs_we_i,

input [3:0] wbs_sel_i,

input [31:0] wbs_dat_i,

input [31:0] wbs_adr_i,

ANKI REDDY SAI PRAVEEN

10/10/2023, 5:32 AM

hi @Matt Venn, can you please explain...?

Matt Venn

10/10/2023, 1:13 PM

take a look at the verilog file that drives them, that should explain

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