JC
09/27/2023, 7:20 PMext2spice cthresh 0, extresist tolerance 10
). Loading the test bench is taking an excruciating long time, which it is still loading (start time: 02:57pm EST) the circuit. I have set within the .spiceinit
file with ngbehaviour=hsa
. Is there a way to speed up this process or a different way to go about this?Harald Pretl
09/27/2023, 7:24 PMcthresh 0
? I would think that something like ext2spice cthresh 0.01
would be more than sufficient.Harald Pretl
09/27/2023, 7:24 PMext2spice rthresh 100
in my PEX script.JC
09/27/2023, 7:34 PMcthresh 0
within Magic equals to all possible parasitic capacitor, is that accurate? Is there a method to figure out what cthresh or rthresh values to use; if its trial and error, do you change the values based on circuit/simulation run time?JC
09/27/2023, 7:55 PMcthresh 0.01
and extresist tolerance 10
, are there any settings that I should be looking out for?
flatten cellname_flat
load cellname_flat
extract all
ext2sim labels on
ext2sim
extresist tolerance 10
extresist
ext2spice lvs
ext2spice cthresh 0
ext2spice extresist on
ext2spice
JC
09/27/2023, 8:18 PMHarald Pretl
09/28/2023, 6:53 AMJC
09/28/2023, 2:15 PMiic-osic-setup.sh
to be able to use iic-pex.sh
properly?Harald Pretl
09/28/2023, 5:21 PMiic-pex.sh
JC
10/20/2023, 10:11 PMiic-pex.sh
. I would like to ask whether I need to have the flat version of the cellname included or I can just use the hierarchal one? Plus, if full R-C mode produces a .spice file of 35MB, is this a point where I should give up on having the parasitic resistances included?