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Hello everyone, I'm trying to create a layout from a Verilog file, but there is an error in synthes...
# openlane
c
Hello everyone, I'm trying to create a layout from a Verilog file, but there is an error in synthesis. It says, "Problems in 'check-assert'." However, I don't know what it means. Do you have any ideas?
m
My guess is that with the 
check -assert
option, 
Lumon2.\clk_out
being used (as input) but not having a driver (it’s not an output) is causing a fatal error.
c
I will check it
but on Vivado the synthesis is good
I delet clk_out but I have an other issue.
m
What does the log file say?
c
ABC : Error : The network is combinational.
I saw I can use with this: set ::env(SYNTH_STRATEGY) {DELAY 1} but it give an error when I lunch with it, I suppose it doesn't like the syntax
m
Are you using 
config.json
or 
config.tcl
?
c
config.tcl,
I think I forget somthing
ok the issue " The network is combinational." is solved but I have another problems
y
@Charly Meyer Could you please share the steps you took to get around the error?? Thanks for the help.
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