Hi all, Can someone guide me on how to simulate gate level verilog code generated by openlane to ch...

ANKI REDDY SAI PRAVEEN

09/18/2023, 12:17 AM

Hi all, Can someone guide me on how to simulate gate level verilog code generated by openlane to check functionality using a testbench

Matt Venn

09/18/2023, 3:25 PM

Hi Anki,

Matt Venn

09/18/2023, 3:27 PM

check this repo: https://github.com/mattvenn/gate_level_simulation

ANKI REDDY SAI PRAVEEN

09/18/2023, 6:48 PM

Thank you @Matt Venn. Can you please suggest me on how to do post synthesis simulations to verify output and how to change the above files to work for my specific design

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