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When I'm doing gate level simulations using iverilog my results are not matching with original resul...
# openlane
a
When I'm doing gate level simulations using iverilog my results are not matching with original results. What might be reason..? @Mitch Bailey
m
Are the results slightly different or entirely different? Have you included the standard cell and macro verilog libraries?
a
I included sky130_fd_sc_hd.v and sram_macro and primitives. Results are entirely different
Im using following commands to execute in iverilog Im using following commands to execute in iverilog 
iverilog fsm_adder.v adder_fsm_tb.v sky130_sram_1kbyte_1rw1r_32x256_8.v sky130_fd_sc_hd.v primitives.v
vvp a.out
gtkwave dump.vcd
fsm_adder.vprimitives.vsky130_fd_sc_hd.vadder_fsm_tb.vsky130_sram_1kbyte_1rw1r_32x256_8.v
I encountered following warnings while doing that. Why is this happening? Please provide a solution for this
m
You might want to ping the channel again. I’m barely literate in verilog.
a
okay.Thank you @Mitch Bailey
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