Hi everyone, I have successfully synthesized my design using Yosys and the sky130_fd_sc_hd process. Now, I'm looking to perform gate-level simulation on the synthesized design using Verilator. However, most of the examples for gate-level simulation use Icarus Verilog (iverilog) as the simulator. I'm wondering if anyone has experience with gate-level simulation using Verilator. Could someone please provide guidance or share their experience? Thank you.

It's also worth pointing out that Verilator is cycle-accurate rather than the proper gate-level timing you might find from Icarus

Thanks for your reply. I am also aware of the cycle-accurate property of Verilator instead of the event-driven simulation of the Icarus Verilog. However, at the beginning, I think if Verilator can verify the functionality of the synthesized circuit, then its ok for me. However, it seems to be problematic when handling gate-level simulation.

Hi Edan, I want to ask you, how you set --bbox-unsup option for Verilator? In config.json? There is an option in configuration.md LINTER_DEFINES https://github.com/The-OpenROAD-Project/OpenLane/blob/master/docs/source/reference/configuration.md I did not understand exactly how to set --bbox-unsup with LINTER_DEFINES

@Burak Aykenar I am using the Verilator directly, not by using the OpenROAD. I compiled my design using the cmake. Therefore, the

--bbox-unsup

arguments is defined in the

CMakeLists.txt

. The following part is the verilate cmd I used in the

CMakeLists.txt

verilate(
	${TOP_NAME}_tb ${TRACE_FORMAT}
	TOP_MODULE ${TOP_NAME} PREFIX V${TOP_NAME}
	INCLUDE_DIRS ${RTL_DIR} ${VOUT_DIR} ${TECH_DIR} SOURCES ${RTL_SOURCES}
	DIRECTORY ${VOUT_DIR} VERILATOR_ARGS ${VARGS}
)

Where the

--bbox-unsup

is set in the

VARGS

using

set(VARGS --bbox-unsup)

Thank you Edan, I found in openlane a new configuration option related to black boxes: VERILOG_FILES_BLACKBOX So I defined primitives.v and sky130_fd_sc_hd.v as VERILOG_FILES_BLACKBOX and then linter does not throw an error