Can the verilog contain sequential blocks? are they supported in the caravel project repositry? I am asking this because my design contains sequential blocks

I have seen Yosys handle sequential code in verilog. I would say that if you can run a full SDF-annotated simulation on the gate-level netlist and it works, then it's okay. But you need to be a bit vigilant about it. I have tried encouraging the AI to generate only synthesizable verilog, but the AIs don't seem to have a particularly good grasp of that concept.