Hi, For the outside data part, I wanted it to go through my design that is in the user space, so the wishbone should be helpful? Ex: gpio -> my design > wishbone slave on user project -> wishbone on processor -> processor please do tell me if this is a feasible one

Yes, This is absolutely possible. There is one thing to be aware of: 1)The clock source on the board driving data into the GPIO should be either of known phase and frequency relation ship to the on chip clock or 2) you must go through a clock synchronizer as you through the interface from outside the chip to your logic or 3) you must synchronize between your logic and the wishbone bus, It is absolutely doable and common in many designs that have been implemented. If the clock has a different frequency and will deliver data out of phase there must be some buffering and storage mechanism at the boundary. The most common are FIFO memories and handshake signals for low data rate interfaces.