Does someone know why this error happens?

Looks like yosys detects these signals being used as input to some logic, but that they are not being driven. Are you using

wbs_ack_o

and

wbs_dat_o[*]

in your rtl? From the i/o specification for

user_project_wrapper

input wb_clk_i,
    input wb_rst_i,
    input wbs_stb_i,
    input wbs_cyc_i,
    input wbs_we_i,
    input [3:0] wbs_sel_i,
    input [31:0] wbs_dat_i,
    input [31:0] wbs_adr_i,
    output wbs_ack_o,
    output [31:0] wbs_dat_o,

wbs_ack_o

and

wbs_dat_o

are outputs of

user_project_wrapper

so if you’re using them as input for some logic, you’re also going to have to drive them.

No, I'm not using that signal. I added the command "QUIT_ON_SYNTH_CHECKS": 0, to my config file and the synthesis finished successfully, but is adding that variable correct or does it affect system synthesis?

@Emilio Baungarten The screen shot only shows `Warning`s. Are there also actual errors? Can you share your entire error log with

"QUIT_ON_SYNTH_CHECKS": 1

?