hi all during LVS i am getting this issue fanout node counts mismatches. i have checked it multiples times fanout is fine, still getting this issue. all relevent files are attached. i am doing LVS of PFD_t2 and PFD_ver_2.
How this can be corrected, or where can I check this
m
Mitch Bailey
08/07/2023, 9:17 AM
Make sure
Simulation
->
Use 'spiceprefix' attribute
checked?
a
Atif Khan
08/08/2023, 3:41 AM
I checked spiceprefix is X, secondly I have two layout of same circuit, first one is working with same netlist second one is not working ( second one is re-iteration although functionality wise first one was working just to give good look I created second one ) so I don't think schematic netlist have any sort of problem
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