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Hello everyone! Please I'd like to know what I'm doing wrong? I'm new to layout. I'm trying to do ...
# analog-design
e
Hello everyone! Please I'd like to know what I'm doing wrong? I'm new to layout. I'm trying to do a quick layout for a single-stage operational amplifier using Magic VLSI tool. I completed the layout without DRC error. I extracted the spice netlist and I discovered that all the node(drain, gate, source, bulk) for each transistors were just reading VDD. For now I'm not bother whether the layout has been done in an optimised way or if the layout has used up the best minimum area it can. I'm concerned with the routing for now. I think I'm having issues with the routing and using the right metal or via material. Please correct me if I'm wrong with what I think. Please I need help. I've attached the extracted spice netlist, the layout and the schematics. The GF180 technology was used for the layout. Thank you.
l
Locali metal you're using to connect to the transistor diffusions is passing over the substrate terminal of the PMOS devices, which is connected to the guard ring.
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You must use more than one metal layer.
k
@Emmanuel Innocent You can check for these sort of layout errors by running LVS (layout versus schematic)
e
@Luis Henrique Rodovalho thank you. But it seems I would not be able to do the routing without passing over the substrate terminals.
Please, pointing me to a comprehensive material on basic analog design layout would be appreciated.
l
You're using the locali layer. if you use vias, you can make take your routing signals to metal1 and pass over the substrate connections, without making a short. Check this tutorial:

https://www.youtube.com/watch?v=CSZm3q4rUBgâ–¾

Here, the same circuit, but using transistor arrays. Try to use the other metal layers.
e
@Luis Henrique Rodovalho thank you very much for the materials and example. Since I'm using GF180 technology, I changed the skywater tech command in the amp0.mag file. I had watched the video but I still have some doubts. I don't clearly understand why and how I should use different metal layers. The +ve and -ve power rail seem not to be differentiated in the layout.
l
You need more metal layers because of this: The metal1 routings are passing over the transistor guard ring, which is connected to the nwell. The drain, gate, and source terminals are also connected to the same metal routing.
e
@Luis Henrique Rodovalho thank you very much sir.
Please can I get the schematics for the amp0.mag file if it's available?
l
There are no schematics. The circuit is the one you uploaded, but made with transistor arrays. The transistor dimensions are: M1: 8 x 1:2 x 1.5 um / 0.5 um - Seq = 12 M2: 8 x 1:2 x 1.5 um / 0.5 um - Seq = 12 M3: 8 x 2:1 x 1.0 um / 0.5 um - Seq = 32 M4: 8 x 2:1 x 1.0 um / 0.5 um - Seq = 32 M5: 16 x 1:2 x 1.5 um / 0.5 um - Seq = 24 M6: 16 x 1:2 x 1.5 um / 0.5 um - Seq = 24 I should have made the PMOS a little wider. 1.25 um / 0.5 um 1:2 means two transistors in series. 2:1 means two transistors in parallel.
e
@Luis Henrique Rodovalho thank you very much, sir for the assistance so far. Things are getting clearer. Please sir, I need the design rule reference material that highlights the rules for poly, metal layers, etc. I can't find one on the internet.
l
The design rules for the PDK are here: https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_10.html There are plenty of materials about CMOS layout design. If you want to make any design, you should begin with easier ones, as logic gates as the inverter, or a nand. There are lots of materials about that already.
e
Thank you sir. I've tried simple designs, but it seemed because they were less complex I was able to get away with a one layer routing. I had done the layout and post-layout simulation for CMOS inverter.
Following your instructions on metal layers, the spice netlist I generated after routing is now close to what is expected. However, there are few issues. First I discovered the software could not differentiate source and drain in the netlist. For the differential amp transistors that were defined as 2 fingers, in the netlist, it labels the source of one finger as the drain of the other finger, instead of labelling them as a shared drain as done in the layout.
l
The FET is symmetrical. It doesn't matter if the drain/source are switched after extraction. The simulations should have the same results.
e
Yes that was my expectation too --- symmetry. The lines labelled inverting and noninverting correspond to the diff amp pair. Two fingers were used to define each member transistor of the pair. I was expecting that the fingers that are members of a single transistor in the diff amp pair will be connected to same node -- perfectly in parallel. But taking lines 9 and 10 as example the drain of one finger is connected to the source of another finger; I was expecting a shared drain configuration.
l
It doesn't make a difference for simulations. But, as you can see in your netlist, there is a VSUBS node in your design. It means you haven't connected anything to the substrate. It should be connected to ground. I would call it vss. Try to make your labels ports, so it the extraction makes a subcircuit.
e
Okay sir. I did label the substrate I was also surprised that the generated netlist did not include the labelling. I will check the layout again. Thank you for the insights, sir.
Please how do I make the label ports? Are these the nodes that will have label port: Vdd, Vin+, Vin-, VSS and Vout?
Please, I'd also like to know: typically after layout of this kind of single stage opamp, what are the next chronological processes?
l
To make ports, I just select the label and type this command in the console 
port make
The symmetrical amplifier is the next step. It has the same input range than the simple differential pair, but the output range is extended
The constant gm is a good circuit to begin biasing the amplifiers. There a much better circuits, but you should begin with it
The you have the folded cascode. It has better input range and gain, but the biasing circuit is a bit more complex
Then you design a Miller amplifier. This is the absolute minimum to know about amplifiers. But most of them aren't really used in actual as opamps
The you must learn a more useful topology, as a class AB. http://resolver.tudelft.nl/uuid:d59c343f-3550-4cdf-8e20-c9135ba5d533
e
Thank you very much sir. These will be helpful!

https://open-source-silicon.slack.com/files/U01QTMG2K8R/F05PSKP8P62/image.pngâ–¾

Dear sir, is this topology a 2-stage? Is there any advantage to why the differential stage is done with a pmos?
https://open-source-silicon.slack.com/archives/C016HUV935L/p1693294619220019?thread_ts=1690962642.005079&cid=C016HUV935L I already worked on a folded-cascode topology. But because the biasing was not good, I could not achieve the complete specifications of the design. So I had issues with biasing.
https://open-source-silicon.slack.com/archives/C016HUV935L/p1693294782896759?thread_ts=1690962642.005079&cid=C016HUV935L I'm currently designing a miller opamp. Dear sir, you said this, 
But most of them aren't really used in actual as opamps
Please sir, I'm curious to know why are these not used and the topology that are used in actual opamp design.
l
I consider the symmetrical amplifier a single stage amplifier, but some people consider it a two stage. Its differential pair doesn't have gain. It just mirror the current to another stage, which has gain. It has a better output voltage range than the simple differential pair. You should try designing it.
The folded cascode is a must know amplifier. Learn how to bias it, otherwise, you will have a hard time learning to bias more advanced amplifiers. The key to learn it is learn how to bias cascode current mirrors first.
The problem of the Miller amplifier is that it cannot provide output current efficiently. Let's say that the amplifier from the figure is biased with 10 uA and it is mirror by a 4x factor from m5 to m7. M7 can provide a maximum of 40 uA. M6 is biased also with 40 uA, but it can provide more output current, because its gate voltage is not fixed. This can be a problem for operational amplifier applications with resistive feedback. If you have a 1 kOhm load, you need 1 mA to make a 1 V voltage drop. The previously mentioned Miller amplifier design could output more than 40 mV from the NMOS side. The class AB amplifier can provide more than the biasing current. See, a real operational amplifier uses a quiescent current if the inputs and outputs are the same. However, it can output more current, if the power supply can.
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