How do I retain the actual names of registes? In our design there are D flipflops and fifo registers. After synthesing yosys , renames the flip flops sky130_fd_sc_hd_dfrtp_2 _14258 ( .CLK(CLK), .D(00157), .Q(mv_output[20]), .RESET_B(RST_N) ); When synthesizing Verilog in openlane yosys generates a verilog rtl which consists of 6-digit codes for the registers. Thus most of the registers have unhelpful names such as 14258. How do I retain the actual names of the registers usded in the verilog rtl?

You can do this command before dfflibmap in the synthesis script: rename -wire -suffix _reg t:*DFF* (some more info here: https://github.com/YosysHQ/yosys/issues/3195)