Hi, I have some questions..Thank you for any help ☺️ 1. If I use core_utilizaition on comfig.mk, How core size is defined? Where Can I check their options? 2. I think core utilization=cell size/ core size .. so cell size is reported after yosys synthesis?(I can't found cell size on logs) 3. If I change timing constraint, It affects on pnr? When I changed clk period in constraint.sdc, Nothing changed in final file..(Because yosys does not support timing, timing constraint does not affect to pnr?) 4. When I use core utilization option, there is an error like this.. Why high utilization is possible? How can I raise it? #openroad #openlane