Hello. I have a question of Delay. If worst slack(positive) is high, its mean that delay of architecture is small? I want to check Delay. #openlane

Worst positive slack is probably referring to hold time (@Tim Edwards is that correct?) , that is how much time input data on a flip flop remains stable after clock active edge transition. Flip flops require a setup time and a hold time. Setup time refers to the time before clock edge where data input must remain stable, hold time refers to the time after clock edge. In the interval

[setup : hold]

data must remain stable for correct behavior of your logic. The bigger the setup and hold time of your data w.r.t. the flop the better. Setup violations (data not ready) can be fixed by lowering the clock frequency. Hold time violations (input data changes before flop has a chance to acquire it) can NOT be fixed by lowering clock frequency. You must either eliminate clock phase differences between flops (clock tree balancing) or delay the data coming into that specific flop. These fixes usually require a new silicon (perhaps only with some new metal masks to use some spare logic) or (in case of FPGAs) re-synthesis. A good standard cell library usually should have flops that even if daisy chained together with minimal metal line (shift register) and driven by the exact same clock phase should work with no hold violations. Setup violatoins occur when raising frequency above a certain value that represents the limit of your circuit.

Thankyou so much!