Hi, I think I have a problem with my drc macro launches with Klayout. Line 491: The via width should be 0.15, not 0.14. A DRC error (m2.5) is found in the celle via generated, there is normaly no error inside. When I replace 0.14 with 0.15, the DRC error is not present Do you have any idea why that's a problem? And where can I find a DRC rule for sky130? Thanks for your help

https://skywater-pdk.readthedocs.io/en/main/rules/periphery.html This is convoluted check. The design rule is that via must be enclosed by m2 on at least 2 opposite sides by 0.085um. To detect this error, via edges with less than 0.085um are selected. These via edges are subtracted from all via edges, leaving via edges with enclosure >= 0.085um. A temporary “good” via is created from a width “error” between these via edges. Vias that are not “good” vias are output as errors. As you reported, the temporary “good” via should be created with a width slightly greater than the via size. @Amro Tork Can you check this?

The via must be equal to 0.15 µm x 0.15 µm. When I create a via with dimensions of 0.14 µm x 0.14 µm, I have no error for M2.5, which states "M2 enclosure of two opposite edges: 0.085 µm." However, I do receive an error indicating that the size of the via is not equal to 0.15 µm x 0.15 µm.