@Tim Edwards, Could you please help me find data about the drain area of Skywater's NFETs and PFETs? Right now, I'm using Klayout to measure the area of the drain for NFET and PFET by manually measuring the length and width of the drain layout. I'm not sure if that's right. Could you please help? Thanks.

It is almost never the case that source and drain area are going to make a significant difference to your circuit. Generally, you would want to take the estimated values from xschem (which are based on gate width) and use them for design simulation, and then later extract the netlist from Magic to get the exact values of all transistor source and drain areas and perimeters. There should never be any need to measure them manually.

Okay, that makes sense. Thank you for the suggestion!