Hello everyone, I tried to harden the user_project_wrapper as a unique and flat design, trying to do that, I instantiated my design in the user_project_wrapper, then I added the path of the module at VERILOG_FILES variable and eliminated some configuration variables (MACRO_PLACEMENT_CFG, EXTRA_LEFS, EXTRA_GDS_FILES, and VERILOG_FILES_BLACKBOX). This didn't work, My question is how can I harden the user_project_wrapper with option 2 mentioned in the documentation?

Many of the parameters in

user_project_wrapper/config.json

are for option 1 only. In order to enable option 2, refer to the parameters in

user_proj_example/config.json

. Specifically, you might want to set some or all of these.

"SYNTH_ELABORATE_ONLY": 0,
    "PL_RANDOM_GLB_PLACEMENT": 1,
    "PL_RESIZER_DESIGN_OPTIMIZATIONS": 1,
    "PL_RESIZER_TIMING_OPTIMIZATIONS": 1,
    "PL_RESIZER_BUFFER_INPUT_PORTS": 1,
    "FP_PDN_ENABLE_RAILS": 1,
    "DIODE_INSERTION_STRATEGY": 2,
    "RUN_FILL_INSERTION": 1,
    "RUN_TAP_DECAP_INSERTION": 1,

Thanks David that works. In addition to those settings I have added "IO_SYNC": 0, I think that is a caravel parameter isn't it?

I wasn’t able to find

IO_SYNC

in https://openlane.readthedocs.io/en/latest/reference/configuration.html, but glad to hear it worked.