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hi everyone! i tried modify clock period to 400,  cap margin 40 to fix hold time violation.. but still it has violation.
Also it represent Error 134 after make finish. What could i do? Thanks for any help :joy:

Thanks so much! i used example nangate45/swerv <http://config.mk|config.mk> file! My goal is no error make and no violation..

export DESIGN_NAME = swerv
export PLATFORM    = nangate45

export VERILOG_FILES = ./designs/src/$(DESIGN_NAME)/swerv_wrapper.sv2v.v
export SDC_FILE      = ./designs/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc

export CORE_UTILIZATION = 40
export CORE_ASPECT_RATIO = 1
export CORE_MARGIN = 5

export PLACE_DENSITY_LB_ADDON = 0.20

I defined cap_margin and slew_margin on floorplan.tcl! 

<@U0268926L04> Thank you so much! I defined CAP_MARGIN and SLEW MARGIN on <http://config.mk|config.mk> and it works!

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