It didn't work on it's own, I tried changing the gpio_config_io from C_USER_OUT to C_MGMT_IN, but that also doesn't work (and stops any user output from getting out of the chip). Is there a C_MGMT_MONITOR or similar I could use?

Is this related to the

io_oeb

issue? Is

io_oeb[*]

low when you want to output?

there's not a problem with the design getting data out of the ios (io_oeb is low for all outputs). The issue is that I can't find a way for the management core to read that data being output. Here's an example firmware that shows it should work: https://github.com/efabless/caravel_user_project/blob/3a71fab0255a5eea4311f453e6ea95e7f16a992e/verilog/dv/mprj_stimulus/mprj_stimulus.c#L127

@Matt Venn: I'd have to go stare at the code to be sure the values are correct and that it works the way I think it does, but the general concept was this: The GPIOs (on everything up to and including MPW-8; MPW-9 and forward is done differently and none of this applies) have a 1-wire data interface and both the housekeeping and management have to agree which way the data flows. If you set it in the configuration to OUTPUT, then data goes from houskeeping or the user project to the GPIO. If you set it to INPUT then the data goes from the GPIO to the user project or housekeeping. But the "monitoring" function is different: You want to set up the GPIO for OUTPUT for the user domain, but INPUT for housekeeping. So what you need to do is to (1) set the configuration for USER OUTPUT, (2) program the GPIO, (3) set the configuration for MANAGEMENT INPUT (without programming that into the GPIO). Then the GPIO is configured for USER OUTPUT, but the management thinks that it is an input and can monitor the value accordingly. I'm not sure it's even necessary to use C_MGMT_MONITOR, though that should work. The main thing is to have different configuration settings at the GPIO and inside housekeeping.

what changed on MPW8 and onwards?

We realized that the single-wire interface needed long wires but couldn't be buffered in the middle for signal integrity. There seemed to be plenty of room for running twice as many wires, so I just changed them all to 2-wire interfaces, so neither side has to worry about what direction the data goes.

poor man solution if you spare I/O: use jumper cable between managements input and user project outputs ? :)