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Is using the logic analyzer as simple as reading the reg_la0_data to reg_la3_data registers or does it require initial setup?

You need to set up the `oenb`/`iena` to be whichever direction of LA you're using

here's an example

```// Configure LA[63:0] as userproj -&gt; caravel
// Configure LA[127:64] as caravel -&gt; userproj
reg_la0_oenb = reg_la0_iena = 0x00000000;    // [31:0]
reg_la1_oenb = reg_la1_iena = 0x00000000;    // [63:32]
reg_la2_oenb = reg_la2_iena = 0xffffffff;    // [95:64]
reg_la3_oenb = reg_la3_iena = 0xffffffff;    // [127:96]```

also you'd read from `reg_la0_data_in` and write to `reg_la0_data`, they're two different registers

everything's done at a bit-granularity so i.e. the bits you set as outputs will be dont-cares in the `_data_in` register and vice versa

Great! Thanks for your reply. How did you aquire this information? I find the documentation of logic analyzer is very thin.

there's this readthedocs page which has some info

<https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/index.html#logic-analyzer>

that plus digging thru the header files in the firmware repo